How to extract Timescale information from a HUGE design

Srinivasan Venkataramanan

srinivasan_v@india.com

-Introduction-

1. This is my first PLI application. I am learning PLI currently and thought would start with the latest version (I always prefer new stuff) so statrted with PLI 2.0 (VPI).
   
   Later on I found that it is not supported by all the major EDA Vendors (:-
   
   Nevertheless I hope things will change and hence decided to proceed with VPI.

2. This application just walks through the complete hierarchy and spits out the Timescale information for each module. I got the idea of developing this via Comp.Lang.Verilog News Group. Some one was trying to find which module has the least timescale precision value
   (and hence controls the whole simulation) and unfortunately that part was "encrypted"!.
   But fortunate enough he was using VCS, wherein there is an option of " -Xman=4 " which would spit out the complete design into a single file " tokens.v ".
   
   Well, he had solution, but I thought "Why don't I take up this task as my first excercise in writing PLI"?, the result...this page :-)
   
   I am not sure how much useful this is to you (if at all it is) in a real application, but may be if there is a novice PLI programmer, he/she may find it interesting :-)

-Description-

Sometimes one might wish to see the information about the Timescale in a HUGE design (for e.g. when the design has been given as a compiled database or a protected one). This application will extract:

1. The module name
2. Its Time Scale value
3. Its TimePrecision value.

   I have developed a PLI task named " $print_timescale " which if called on a top level module will print this information for the entire hierarchy.

   The following Verilog code (which could be the top level of your design, or TB) shows how to use such a call.
   

 `timescale 1 us / 1 ps;
   
 module top;

 wire q;
	 
 block1 u1 (q, clk, a, b);
 block2 u2 (out_val, clk, a, q);

 initial
   $print_timescale;

endmodule

`timescale 1 ns / 10 ps;
module block1 (q, clk, a, b);
output q;
input clk, a,b;

// Description..

endmodule

`timescale 1 ps / 10 fs;
module block2 (q, clk, a, b);
output q;
input clk, a,b;

// Description..

endmodule